I myself Talha Ahmed an undergraduate final year student of Software Engineering from Usman Institute of Technology. I got an opportunity this summer to contribute to open-source project of UC-CROSS by Google Summer of Code 2022.
This work presents an extension of the OpenRAM memory compiler to provide the automated generation of latch-based register files. It uses standard cells from the Skywater 130nm library. OpenRegFile automatically generates a spice netlist, layout, and a verilog model. It leverages the hierarchical decoders and muxes from SRAM designs. The cells for the decoders and muxes in SRAMs are custom made but we replace them with standard cells to improve routability and portability to other technologies with a cell library. At first, we created a register file array along with a tristate. The tristate helps to use the same data-line throughout the array of D-Latches which improves routing. We used the spice netlist API to implement the logic in OpenRAM and created custom modules to create the layout.
Introduction to OpenRAM:
An open-source SRAM-based memory compiler called OpenRAM automatically compiles and creates models for routing, placement, timing characterization, and layout. With fabricable technology, it enables both open-source and commercially available processes. It eliminates the requirement for open-source memory compilers by leveraging easily available Process Design Kits to meet the demands of computer architecture research (PDKs).
OpenRegFile is an extension of OpenRAM which will be used to compile register files. It will create a D-Latch based Register File by using standard library cells of Skywater 130nm and generate its Spice netlist, layout, Verilog model.
Initially implemented the logical schematic of the Register File in Logisim tool for better understanding the structure of it, which helps us to implement the logic of register file in OpenRAM. Fig A. is a 2W1R Register file having 4 rows and 5 columns of latches. It uses the same data-line by using tristate for better routing. It uses Main-Subsidiary latch architecture for power efficiency and to prevent data race-around condition.
Created a register file array along with a tristate. The tristate helps to use the same data-line throughout the array of D-Latches which improves routing. Fig B. is generated latch array of 5 rows, and 3 columns, with tristate and well taps every two latches in a row.
Spice netlist API is used to implement the register file logic in OpenRAM with the help of a logical circuit from the first step and created custom modules to create the layout.
The available cells for the decoders and muxes in OpenRAM are custom made but we replace them with standard cells to improve routability and portability to other technologies with a cell library. Fig C. 2x4 Decoder using standard cells of NAND and INV.
Following that, Magic VLSI layout editor is used to verify as to whether a specific design meets the constraints imposed by the process technology to be used for its manufacturing by using DRC. Netgen is used to ensure the functional correctness of the design by LVS.
All the cells used in this project are from the Skywater 130 nm standard cells library.
- dlxtn (Delay latch, inverted enable, single output)
- tapvpwrvgnd (Substrate and well tap cell)
- einvn (Tristate inverter, negative enable)
- nand2 (Two input NAND)
- nand3 (Three input NAND)
- nand4 (Four input NAND)
I would like to thank my mentors Mathew R. Guthaus and Jesse Cirimelli-Low always support me and guide me about any issue which I’ve faced during the project.